Description

Cadence Conformal Low Power is a power intent creation and verification solution designed for designers and manufacturers. It enables users to optimize the risk of silicon re-spins, detect low-power implementation errors, verify and debug multi-million-gate designs, consolidate logic equivalence checking for low-power SoC and datapath intensive designs, create, validate, and integrate power intent in the context of the design, establish macro models for IP or a level of the hierarchy, as well as validate post-synthesis netlist. Features include risk optimization, common power format (CPF) specification language support, retention management, domain assignment management, and Verilog support.