Description

Cadence JasperGold Formal Verification Platform is a design process verification solution designed for design engineers. It enables users to track end-to-end packet integrity by detecting dropped, duplicated, or corrupted data, calculate the minimum signal activity needed to exhibit the behavior in question, analyze the fault list for untestability, verify data sanctity and fault-tolerant security, modify or create properties to explore design behavior, as well as perform structural, functional, and sequential checks. Features include what-if analysis, bug hunting, SystemVerilog Assertion (SVA), collaboration management, and optional configuration controls.