Description

Cadence Modus DFT Software is a design-for-test (DFT) solution designed for circuit design engineers. It enables users to handle multiple shift cycles to control register values in a single fault-capture cycle, form a physically aware 2D grid across the design floorplan, simulate multiple defect types concurrently, reorder compressed/uncompressed patterns, update coverage by targeting hard-to-test faults caused by high-care bit requirements, as well as scan and capture toggle-rate controls. Features include programmable memory built-in self-test (PMBIST), timing-aware test point insertion, XOR compression logic, 2.5/3D stacked die wrapper, and on-product clock generation (OPCG).