Description

Power Compiler is a gate-level power optimization and synthesis solution designed for register transfer-level (RTL) designers. It enables users to perform clock gating and low power placement to reduce dynamic power consumption, manage concurrent multi-corner multi-mode based optimization, measure the trade-offs between positive timing slacks, area, and power, automatically input the power management cells such as isolation, level-shifter, retention register, and power gating, and automate the implementation of unified power format (UPF) advanced low power techniques. Features include multi-voltage threshold-based optimization, user-instantiated clock gating, dynamic voltage and frequency scaling (DVFS), design flow management, and state retention.