Description

Synopsys PrimePower is a block-level and full-chip design power analysis solution designed for register transfer level (RTL) designers. It enables users to analyze, explore, and optimize the RTL design cycle, build a timing-aware power profile of the design based on connectivity, switching activity, net capacitance, and cell-level power behavior data, calculate concurrent reading of RTL and gate-level vectors from simulation and emulation, examine the RTL blocks, subsystems, and full-SoCs, and generate files for implementation power recovery and ECO signoff. Features include multi-voltage power analysis, reporting capability, waveform visualization, glitch analysis, peak power analysis, and context-aware leakage.