Description

Synopsys VC Formal is a comprehensive verification and debugging solution designed for semiconductor sectors. It enables users to access outcome to verify SystemVerilog Assertion (SVA) properties, manage property browsing, grouping and filtering, accomplish custom optimizations and engines for datapath verification (ALU, FPU, DSP) using transaction-level equivalence, automate functional analysis with conflicting and floating bus checks, as well as leverage investigation with source code browsing and analysis reporting. Modules include assertion-based property verification, datapath validation, formal coverage analysis, connectivity checking, sequential equivalency checking, and regression mode accelerator.