Description

Synplify is a suite of field-programmable gate array (FPGA) synthesis tools designed for design engineers. These products enable users to detect functional errors in FPGA designs that are operating on the board, automate the gated clock conversion for FPGA-based prototyping, perform design diagnosis, problem isolation, and functional and performance analysis, instrument and debug FPGA design directly from RTL source code, and traverse the debug sample buffer like a simulator environment. Products include Synplify Pro, Synplify Premier, and Identify RTL Debugger. Features include integration with VCS Simulator, DSP inference, automatic memory, graphical state machine viewer, and interactive graphical analysis.